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Category: List of Bases 2008 2008 ICTP activities outside Trieste ICTP activities outside Trieste
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lecture

Start Time:

16 June 2008 at 08:15

Ends On:

11 July 2008

Location:

Kuala Lumpur - Malaysia

Organizer(s):

Directors: M.B.I. Reaz, S.C. Ng, A. Cicuttin, N. Abdallah, A. Marchioro, M.A.M. Ali, F. Mohd-Yasin, C. Oh, A.A. Halim

Description:

This Workshop will be live broadcasted through MYREN via mms://streaming.myren.net.my/ictp. To view the lectures and lab sessions in real time it is necessary to be connected to the local REN (Research and Development Network).
This is done on experimental basis.




Material:

VENUE: Main Auditorium, Kulliyyah of Engineering, IIUM
16 June 2008
08:15
09:30
REGISTRATION AND ADMIN FORMALITIES
01h15'
09:30
10:15
Altera-MDEC FPGA Education Launch
45'


Speech by Tn. Hj. Fadillah b. Hj. Yusof, Deputy Minister of Science, Technology & Innovation  10'
Speech by Datuk Ir. Hj. Idris bin Hj. Harom, Deputy Minister of Higher Education   10'
Memorandum of Understanding Exchange Ceremony between CEO MDeC and VP Altera  10'
Launch Video presentation on MDeC-Altera Industry-Academia Collaboration  05'
Adjourned for Press Conference  10'
10:15
10:30
Break
15'
10:30
11:30
Introduction
01h00'


IIUM  05'
Prof. Dr. Ahmad Faris Ismail  (Dean, Faculty of Engineering )
TARC  05'
S.C. Ng  (Head, School of Science)
ACTEL  05'
Representative
ALTERA  05'
Representative
EMERALD Sys  05'
Representative
MYREN  05'
Representative
SHRDC  05'
Representative
INTEL  05'
Ong Sze Wei  (Design Automation Manager, Penang Design Center (PG12))
SYNOPSIS/TRANSDIST  05'
Sreedharan Baskara Dass  (Senior Application Engineer)
CADENCE  05'
Representative
11:30
11:45
Break
15'
11:45
13:00
Opening Ceremony
01h15'


International Islamic University of Malaysia (IIUM)  10'
Y.Bhg. Prof. Dato' Dr. Syed Arabi Idid  (Rector, IIUM)
TARC  10'
Yoong Lai Thye  (Principal)
ICTP  10'
C. Tuniz  (Assistant Director, ICTP)
AAAPT  10'
C.S. Wong  (President, Asian African Association for Plasma Training (AAAPT))
Official launching  15'
Y. Bhg. Dato' Dr. Halim Man, Chief Guest  (Secretary General, KTAK)
13:00
15:00
Opening Lunch
02h00'
15:00
15:30
Course Overview
30'
Nizar Abdallah, Andres Cicuttin
ACTEL, ICTP
15:30
16:30
Effective FPGA/VLSI Education Techniques
01h00'
Stephen Brown
Director, Altera University Programme
16:30
17:00
Break
30'
17:00
18:00
Introduction to FPGA Synthesis, Introduction to VHDL.
01h00'
Nizar Abdallah
18:00
19:00
Introduction to Digital Design (Boolean logic)
01h00'
Pirouz Bazargan-Sabet
20:00
22:00
Dinner
02h00'
VENUE: IIUM
17 June 2008
09:30
10:30
Introduction to ACETEL Products. Libero IDE Overview and Design flow
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Synthesis I - Introduction to VHDL
01h00'
Nizar Abdallah
12:00
13:00
Synthesis II - Introduction to VHDL
01h00'
Nizar Abdallah
13:00
15:00
Lunch
02h00'
15:00
16:00
(LiberoTM IDE) Design Entry
01h00'
Nizar Abdallah
16:00
16:30
Break
30'
16:30
17:30
Digital Design I (combinatorial elements)
01h00'
Pirouz Bazargan-Sabet
17:30
19:00
Digital Design II (sequential elements, Mealy and Moore FSM)
01h30'
Pirouz Bazargan-Sabat
20:00
22:00
Dinner
02h00'
VENUE: IIUM
18 June 2008
09:30
10:30
(LiberoTM IDE) Functional Simulation. Synthesis
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Synthesis III - Advanced VHDL
01h00'
Nizar Abdallah
12:00
13:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
01h00'
Pirouz Bazargan-Sabat
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. VHDL Simulation Environment. A design example
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. VHDL Simulation Environment. A design example. Contd.
02h30'
Maria Liz Crespo
19:00
21:00
Dinner
02h00'
VENUE: IIUM
19 June 2008
09:30
10:30
(LiberoTM IDE) Place & Route
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Digital arithmetic I (number representations)
01h00'
Pirouz Bazargan-Sabet
12:00
13:00
Digital arithmetic II (basic arithmetic operations)
01h00'
Pirouz Bazargan-Sabat
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. VHDL Behavioral Description and Simulation of Combinational Circuits. Contd.
02h30'
Maria Liz Crespo
20:00
20:00
Dinner
VENUE: IIUM
20 June 2008
09:30
10:30
Design Verification and Timing Concepts
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
(LiberoTM IDE) Timing Constraints and Analysis
01h00'
Nizar Abdallah
12:00
13:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
01h00'
Maria Liz Crespo
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. VHDL Behavioral Description and Simulation of Sequential Circuits
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:30
Laboratory Session. Finite State Machine: VHDL Description and Simulation
03h00'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: IIUM
23 June 2008
09:30
10:30
Programmable logic & FPGA architectures
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
(LiberoTM IDE) Post-Layout Simulation. Programming
01h00'
Nizar Abdallah
12:00
13:00
Microelectronics at CERN
01h00'
Paulo Moreira
13:00
15:00
Lunch
02h00'
15:00
16:00
Introduction to CMOS technology and VLSI design
01h00'
Paulo Moreira
16:00
16:30
Break
30'
16:30
17:30
CMOS Technology I
01h00'
Paulo Moreira
17:30
19:00
Laboratory Session. Parking Lot: VHDL Description, Simulation, Synthesis and Post-Synthesis Simulation
01h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: IIUM
24 June 2008
09:30
10:30
Actel Flash FPGA architecture
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
System-on-Chip concepts
01h00'
Nizar Abdallah
12:00
13:00
CMOS Technology II
01h00'
Paulo Moreira
13:00
15:00
Lunch
02h00'
15:00
16:00
VLSI Design I
01h00'
Paulo Moreira
16:00
16:30
Break
30'
16:30
17:30
Advance FPGA Applications
01h00'
Alexander Kluge
17:30
20:00
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example.
02h30'
Carlos Sosa Paez
20:00
22:00
Dinner
02h00'
VENUE: IIUM
25 June 2008
09:30
10:30
DEMO Actel Fusion Evaluation Board
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
VLSI design II
01h00'
Paulo Moreira
12:00
13:00
Advance FPGA applications. A case study in HEP experiments
01h00'
Alexander Kluge
13:00
15:00
Break
02h00'
15:00
16:00
Advance FPGA applications. A case study in HEP experiments (contd)
01h00'
Alexander Kluge
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. Hardware Description of the FPGA Development Platform. FPGA Implementation Example. (cont)
02h30'
Carlos Sosa Paez
20:00
22:00
Dinner
02h00'
VENUE: IIUM
26 June 2008
09:30
10:30
Introduction to Fourier Theory
01h00'
Marcelo Magnasco
10:30
11:00
Break
30'
11:00
12:00
Fourier Theory I
01h00'
Marcelo Magnasco
12:00
13:00
Fourier Theory II
01h00'
Marcelo Magnasco
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation in the FPGA Development Platform (cont)
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. Synthesis, Pos-Synthesis Simulation and Implementation on the FPGA Development Platform (cont.)
02h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: IIUM
27 June 2008
09:30
10:30
Introduction to Digital Signal Processing
01h00'
Marcelo Magnasco
10:30
11:00
Break
30'
11:00
13:00
Digital Signal Processing I
02h00'
Marcelo Magnasco
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design.
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. Implementation in the FPGA Development Platform. VHDL Package and Structural Design. Bidirectional Parallel Port Communication.
02h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: TARC
30 June 2008
09:30
10:30
Selected topics on Logic Synthesis and FPGA Debugging
01h00'
Andres Cicuttin
10:30
11:00
Break
30'
11:00
12:00
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
01h00'
Andres Cicuttin
12:00
13:00
Laboratory Session. Implementation in the FPGA Development Platform. Bidirectional Parallel Port Communication.
01h00'
Maria Liz Crespo
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. Implementation on the FPGA Development Platform. Digital Arithmetic (cont.)
02h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: TARC
1 July 2008
09:30
10:30
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. I
01h00'
Khan Javed Iqbal
10:30
11:00
Break
30'
11:00
12:00
Models, Mechanics, and Opportunities for Collaborative Engineering and Design in the New Cyber Age. II
01h00'
Khan Javed iqbal
12:00
13:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA
01h00'
Andres Cicuttin
13:00
15:00
Lunch
02h00'
15:00
16:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
01h00'
Andres Cicuttin
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator.
02h30'
Miguel Risco Castillo
20:00
22:00
Dinner
02h00'
VENUE: TARC
2 July 2008
09:30
10:30
Introduction to two-dimensional digital signal processing.
01h00'
Fabio Mammano
10:30
11:00
Break
30'
11:00
12:00
Two-dimensional digital signal processing I.
01h00'
Fabio Mammano
12:00
13:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generator (cont.)
01h00'
Miguel Risco Castillo
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. RVI Architecture. Integration of new blocks
01h00'
Miguel Risco Castillo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. DEMO: ICTP RVI Platform. Virtual Instruments: Digital Oscilloscope and Waveform Generation.
02h30'
Miguel Risco Castillo
20:00
20:00
Dinner
VENUE: TARC
3 July 2008
09:30
10:30
Two-dimensional digital signal processing II. Three-dimensional deconvolution in FPGA I
01h00'
Fabio Mammano
10:30
11:00
Break
30'
11:00
12:00
Two-dimensional digital signal processing III. Three-dimensional deconvolution in FPGA II
01h00'
Fabio Mammano
12:00
13:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
01h00'
Maria Liz Crespo
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
02h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: TARC
4 July 2008
09:30
10:30
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
01h00'
Maria Liz Crespo
10:30
11:00
Break
30'
11:00
13:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA
02h00'
Maria Liz Crespo
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
01h00'
Maria Liz Crespo
16:00
16:30
Break
30'
16:30
19:00
Laboratory Session. RVI Projects. Digital Signal Processing with FPGA.
02h30'
Maria Liz Crespo
20:00
22:00
Dinner
02h00'
VENUE: TARC
7 July 2008
09:30
11:00
System Design: Is Hardware Becoming Software?
01h30'
Chris Oh
11:00
11:30
Break
30'
11:30
13:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
01h30'
King Keong Wong, Thiam Sin Lai
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
01h00'
King Keong Wang, Thiam Sin Lai
16:00
16:30
Break
30'
16:30
18:00
Laboratory Session. Introduction to designing FPGAs with Quartus II and Altera Development Kits
01h30'
King Keong Wang, Thiam Sin Lai
20:00
22:00
Dinner
02h00'
TARC
8 July 2008
09:30
11:00
Formal Verification Techniques for FPGA
01h30'
Elisha Lye
11:00
11:30
30'
11:30
13:00
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
01h30'
. Jimmy Yeap
13:00
15:00
Lunch
02h00'
15:00
16:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
01h30'
Jimmy Yeap
16:30
17:00
Break
30'
17:00
18:30
Laboratory Session. Designing Systems in Altera FPGAs Using Altera\'s System Level Development Tools.
01h30'
Jimmy Yeap
20:00
22:00
Dinner
02h00'
TARC
9 July 2008
09:30
10:30
An Overview of Microprocessor Architecture &. Implementation of a Large Bus Size VLIW Microprocessor on FPGA
01h00'
Weng Fook Lee
10:30
11:00
Break
30'
11:00
12:00
An Overview of Microprocessor Architecture & Implementation of a Large Bus Size VLIW Microprocessor on FPGA.
01h00'
12:00
13:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
01h00'
Choong Yee Lee
13:00
15:00
Lunch
02h00'
15:00
16:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
01h00'
Choong Yee Lee
16:00
16:30
Break
30'
16:30
18:00
Laboratory Session. Digital Design and Implementation on FPGA Using Mentor Graphics\' FPGA Advantage
01h30'
Choong Yee Lee
20:00
22:00
Dinner
02h00'
VENUE: TARC
10 July 2008
09:30
10:30
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
01h00'
Chew Beng Wah
10:30
11:00
Break
30'
11:00
13:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon
02h00'
Chew Beng Wah
13:00
15:00
Lunch
02h00'
15:00
16:00
Validating the Intel Leading-Edge Architecture Microprocessor during Pre-Silicon.
01h00'
Chew Beng Wan
16:00
16:30
Break
30'
16:30
17:30
Challenges in Low Power Design
01h00'
Jasmine NG
CADENCE
17:30
18:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
01h00'
20:00
22:00
Dinner
02h00'
VENUE: TARC
11 July 2008
09:30
10:30
SYNOPSIS Representative: Variation Aware Static Timing Analysis for sub-65nm ASIC Design
01h00'
10:30
11:00
Break proceed to Sport Complex (UA113)
30'
11:00
13:00
Closing Ceremony (UA113, Sport Complex)
02h00'
13:00
15:00
Lunch
02h00'
15:00
16:00
Certificates of Participation (DK E)
01h00'
16:00
16:30
Break
30'
16:30
18:30
Open Discussion
02h00'
20:00
22:00
Dinner
02h00'
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