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Category: List of Bases 2006 2006 ICTP activities in Trieste ICTP activities in Trieste
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lecture

Start Time:

27 November 2006 at 08:30

Ends On:

22 December 2006

Location:

Trieste - Italy

Venue:

AGH (Giambiagi LH)

Organizer(s):

Directors: N. Abdallah, A. Cicuttin, A. Vacchi

Description:

ABSTRACT:
Advances in Field-Programmable Gate Arrays (FPGAs) have opened the door for use in all types of applications including signal processing and rapid system prototyping. Today, FPGAs are more highly integrated and competitively priced versus other traditional technologies. This provides an exciting new model for research and education, where application ideas can be prototyped in great detail on one or more FPGAs for realistic evaluation.

The aim of this workshop is to introduce the participants to the basic techniques necessary to design FPGA-based digital systems using the VHDL hardware description language. The workshop is geared towards physicists, engineers and computer scientists who wish to incorporate the benefits of FPGAs in their system design. FPGA architecture, design methodologies, VHDL, and basics in digital signal processing will be described, followed by hands-on laboratory projects to reinforce learning. Workshop attendees will be presented with a complete FPGA prototyping system, including boards based on Actel's latest Flash FPGA device and the Libero design suite
______________________________________________

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Material:

08:30
11:45
REGISTRATION & ADMINISTRATIVE FORMALITIES
03h15'
Registration and Administrative Formalities
11:45
12:45
Welcome
01h00'



Claudio Tuniz  (ICTP, Trieste)

Andrea Vacchi  (INFN, Trieste)

Nizar Abdallah  (ACTEL Corp, Mountain View (CA))

Andres Cicuttin  (ICTP, Trieste)
12:45
14:00
Lunch
01h15'
14:00
14:15
Network and Computing Facilities at ICTP
15'
Johannes Grassberger
SCS, ICTP, Trieste
14:15
15:15
Course Overview, Introduction to FPGA Synthesis I, Introduction to VHDL
01h00'
Nizar Abdallah
15:15
15:45
Break
30'
15:45
16:45
(LiberoTM IDE) Introduction to Actel Products. Libero IDE Overview and Design Flow
01h00'
Nizar Abdallah
16:45
17:45
Introduction to Digital Design (Boolean Logic)
01h00'
Pirouz Bazargan-Sabet
LIP 6, University of Paris VI, Paris
09:30
10:30
Synthesis II - Instroduction to VHDL
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Synthesis III - Advanced VHDL
01h00'
Nizar Abdallah
12:00
13:00
Digital Design I (Combinational Elements)
01h00'
Pirouz Bazargan-Sabet
13:00
14:00
Lunch
01h00'
14:30
15:30
Digital Design II (Sequential Elements, Mealy and Moore FSM)
01h00'
Pirouz Bazargan-Sabet
15:30
16:00
Break
30'
16:00
17:00
(LiberoTM IDE) Design Entry
01h00'
Nizar Abdallah
17:00
18:00
(LiberoTM IDE) Functional Simulation. Synthesis
01h00'
Nizar Abdallah
09:30
10:30
Synthesis III - Advanced VHDL (cont.)
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc)
01h00'
Pirouz Bazargan-Sabet
12:00
13:00
(LiberoTM IDE) Place & Route
01h00'
Nizar Abdallah
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
ICTP, Trieste
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session (VHDL simulation environment, simple examples)
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
Telit Communications Spa., Trieste
09:30
10:30
Design verification and timing concepts
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
(LiberoTM IDE) Timing Constraints and Analysis
01h00'
Nizar Abdallah
12:00
13:00
Digital arithmetic I (number representations)
01h00'
Pirouz Bazargan-Sabet
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
18:30
20:00
SMALL RECEPTION
01h30'
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Programmable logic & FPGA architectures
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Digital arithmetic II (basic operations: +,-,*,/)
01h00'
Pirouz Bazargan-Sabet
12:00
13:00
(LiberoTM IDE) Post-Layout Simulation. Programming
01h00'
Nizar Abdallah
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Actel Flash FPGA architecture
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
System-on-Chip concepts
01h00'
Nizar Abdallah
12:00
13:00
Laboratory Session
01h00'
Maria Liz Crespo
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
DEMO Fusion
01h00'
Nizar Abdallah
10:30
11:00
Break
30'
11:00
12:00
Q & A (open discussion)
01h00'
Nizar Abdallah
12:00
13:00
Fourier Theory I
01h00'
Konstantin Lukin
Usikov Institute of Radiophysics & Electronics, Kharkov
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Fourier Theory II
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
12:00
Selected topics on FPGA design I
01h00'
Andres Cicuttin
12:00
13:00
Selected topics on FPGA design II
01h00'
Andres Cicuttin
13:00
14:00
Lunch
01h00'
14:30
15:30
Hardware Description of the FPGA Development Platform
01h00'
Alexander Shapiro
15:30
16:00
Break
30'
16:00
18:00
FPGA Development Platform. Design Examples
02h00'
Alexander Shapiro
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Introduction to Digital Signal Processing
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
12:00
Selected topics on FPGA design III
01h00'
Andres Cicuttin
12:00
13:00
FPGA Debugging
01h00'
Andres Cicuttin
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Laboratory projects: Proposals and discussion
01h00'
Maria Liz Crespo
10:30
11:00
Break
30'
11:00
13:00
Laboratory projects: Proposals and discussion (cont)
02h00'
Maria Liz Crespo
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory projects: Proposals and discussion (cont)
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory projects: Proposals and discussion (cont)
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Digital Signal Processing and Radar applications I
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
13:00
CMOS Technology I
02h00'
Jorgen Christiansen
PH-ED, CERN, Geneva
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory projects: Proposals and discussion (cont)
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
17:00
Laboratory projects: Proposals and discussion (cont)
01h00'
Maria Liz Crespo
17:00
19:00
Laboratory projects: Proposals and discussion (cont)
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Digital Signal Processing and Radar Applications I
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
13:00
CMOS Technology II & III
02h00'
Jorgen Christiansen
13:00
14:00
Lunch
01h00'
14:30
15:30
VLSI design I
01h00'
Jorgen Christiansen
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Digital Signal Processing and Radar Applications III
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
13:00
VLSI design II & III
02h00'
Jorgen Christiansen
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Reconfigurable Virtual Instrumentation I
01h00'
Andres Cicuttin
10:30
11:00
Break
30'
11:00
12:00
Reconfigurable Virtual Instrumentation I
01h00'
Andres Cicuttin
12:00
13:00
Digital Signal Processing and Radar Applications IV
01h00'
Konstantin Lukin
13:00
14:00
Lunch
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
20:00
22:00
Night Laboratory
02h00'
Alberto Cerdeira Estrada
09:30
10:30
Digital Signal Processing and Radar applications V
01h00'
Konstantin Lukin
10:30
11:00
Break
30'
11:00
13:00
Laboratory Session
02h00'
Maria Liz Crespo
13:00
14:00
01h00'
14:30
15:30
Laboratory Session
01h00'
Maria Liz Crespo
15:30
16:00
Break
30'
16:00
18:00
Laboratory Session
02h00'
Maria Liz Crespo
18 December 2006
09:30
18:00
Laboratory Session: Projects and Digital Signal Processing with FPGA
08h30'
Maria Liz Crespo,Alexander Shaprio,Andres Cicuttin
10:30
11:00
Break
30'
13:00
14:00
Lunch
01h00'
15:30
16:00
Break
30'
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