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Category: List of Bases 2010 2010 ICTP activites outside Trieste ICTP activites outside Trieste
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lecture

Start Time:

15 March 2010 at 09:00

Ends On:

31 March 2010

Location:

Mar del Plata - Argentina

Organizer(s):

Directors: A. Cicuttin, N. Abdallah, H. Larrondo, L. H. Tabares. LO: J. Finochietto, C. Gonzalez. ICTP LO: M.L. Crespo.

Description:

Venue: CAECE University


Material:

Monday, 15 March 2010
09:00
11:30
REGISTRATION AND ADMINISTRATIVE FORMALITIES
02h30'
Room: LOBBY, UCAECE UNIVERSITY MAIN ENTRANCE
11:30
13:00
OPENING CEREMONY
01h30'
Room: AULA MAGNA CAECE UNIVERSITY


  05'
Maria Alejandra Cormons  (Vice Rector, CAECE University, Mar del Plata, Argentina)
  05'
Manuel L. Gonzalez  (Dean, School of Engineering, National University of Mar del Plata, FI-UNMDP, Argentina)
  05'
Jorge R. Finochietto  (Course Director and Local Organizer, CAECE University - UCAECE, Mar del Plata, Argentina)
  05'
Hilda Angela Larrondo  (Course Director and Local Organizer, School of Engineering, UNMPD, Mar del Plata, Argentina)
  05'
Lorenzo H. Tabares  (Course Director, Centre of Applied Technologies and Nuclear Development, CEADEN, Havana, Cuba)
  05'
Nizar Abdallah  (Course Director, Actel Corp., Mountain View, CA, USA)
  05'
Maria Liz Crespo  (Course Director, the Abdus Salam International Centre for Theoretical Physics, ICTP, Trieste, Italy)
  05'
Maddalena Pennacchiotti  (on behalf of Fausto Panebianco, the Consul of Italy in Mar del Plata, Argentina)
  20'
Andres Cicuttin  (Course Director, the Abdus Salam International Centre for Theoretical Physics, ICTP, Trieste, It)
13:00
14:00
Lunch
01h00'
14:00
15:00
FPGA Design and VHDL. Overview.
01h00'
Nizar Abdallah
15:00
15:30
Coffee break
30'
15:30
16:30
FPGA Architectures & VHDL. Introduction to FPGAs & FPGA Design Flow.
01h00'
Nizar Abdallah
16:30
17:30
Introduction to Digital Design.
01h00'
Pirouz Bazargan-Sabet
LIP6, University Pierre et Matie Curie, Paris, France
17:30
18:30
Digital Design I (combinatorial elements).
01h00'
Pirouz Bazargan-Sabet
Tuesday, 16 March 2010
09:00
10:00
Digital Design II (sequential elements, Mealy and Moore FSM).
01h00'
Pirouz Bazargan-Sabet
10:00
11:00
FPGA Architectures & VHDL. Introduction to Synthesis.
01h00'
Nizar Abdallah
11:00
11:30
Coffee break
30'
11:30
12:30
Synthesis II - Introduction to VHDL.
01h00'
Nizar Abdallah
12:30
14:00
Lunch
01h30'
14:00
15:00
(LiberoTM IDE) Design Entry.
01h00'
Nizar Abdallah
15:00
16:00
Digital Design III (more complex elements: RAM, ROM, buses, pipeline concept, etc).
01h00'
Pirouz Bazargan-Sabet
16:00
16:30
Coffee break
30'
16:30
17:30
(LiberoTM IDE) Functional Simulation. Synthesis.
01h00'
Nizar Abdallah
17:30
18:30
Synthesis III - Advanced VHDL.
01h00'
Nizar Abdallah
Wednesday, 17 March 2010
09:00
10:00
Digital arithmetic I (number representations).
01h00'
Pirouz Bazargan-Sabet
10:00
11:00
(LiberoTM IDE) Place & Route.
01h00'
Nizar Abdallah
11:00
11:30
Coffee break
30'
11:30
12:30
Design Verification and Timing Concepts.
01h00'
Nizar Abdallah
12:30
14:00
Lunch
01h30'
14:00
15:00
(LiberoTM IDE) Timing Constraints and Analysis
01h00'
Nizar Abdallah
15:00
16:00
Digital arithmetic II (basic arithmetic operations).
01h00'
Pirouz Bazargan-Sabet
16:00
16:30
Coffee break
30'
16:30
17:30
Programmable logic & FPGA architectures
01h00'
Nizar Abdallah
17:30
18:30
(LiberoTM IDE) Post-Layout Simulation. FPGA Programming.
01h00'
Nizar Abdallah
Thursday, 18 March 2010
09:00
10:00
Actel Fusion FPGA architecture.
01h00'
Nizar Abdallah
10:00
11:00
Actel Fusion FPGA architecture (cont.)
01h00'
Nizar Abdallah
11:00
11:30
Coffee break
30'
11:30
12:30
The Actel Fusion Embedded Development Kit
01h00'
Nizar Abdallah
12:30
14:00
Lunch
01h30'
14:00
15:00
The Actel Fusion Embedded Development Kit (cont.)
01h00'
Nizar Abdallah
15:00
16:00
Laboratory Overview. VHDL Simulation Environment. A design example.
01h00'
Maria Liz Crespo
ICTP Multidisciplinary Laboratory, Trieste, Italy
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits.
02h00'
Friday, 19 March 2010
09:00
10:00
System-on-Chip concepts
01h00'
Nizar Abdallah
10:00
11:00
System-on-Chip concepts (cont.)
01h00'
Nizar Abdallah
11:00
11:30
Coffee break
30'
11:30
12:30
Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
01h00'
12:30
14:00
Lunch
01h30'
14:00
15:00
Laboratory Exercises: VHDL Behavioral Description and Simulation of Combinational Circuits (cont.)
01h00'
15:00
16:00
Basic Add and Subtract Operations in VHDL. Case examples.
01h00'
Cristian Sisterna
University of San Juan, Argentina
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits
02h00'
Monday, 22 March 2010
09:00
10:00
Microelectronics at CERN
01h00'
Paulo Rodrigues S. Moreira
CERN, Geneva, Switzerland
10:00
11:00
Introduction to CMOS Technology and VLSI Design.
01h00'
Paulo Rodrigues S. Moreira
11:00
11:30
Coffee break
30'
11:30
12:30
CMOS Technology I
01h00'
Paulo Rodrigues S. Moreira
12:30
14:00
Lunch
01h30'
14:00
16:00
Laboratory Exercises: VHDL Behavioral Description and Simulation of Sequential Circuits (cont.)
02h00'
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: Finite State Machine. VHDL Description and Simulation.
02h00'
Tuesday, 23 March 2010
09:00
10:00
Introduction to Fourier Theory.
01h00'
Marcelo Magnasco
Rockfeller University, NY, USA
10:30
11:30
Fourier Theory I.
01h00'
Marcelo Magnasco
11:00
11:30
Coffee break
30'
11:30
12:30
CMOS Technology II.
01h00'
Paulo Rodrigues S. Moreira
12:30
14:00
Lunch
01h30'
14:00
15:00
VLSI Design.
01h00'
Paulo Rodrigues S. Moreira
15:00
16:00
Laboratory Exercises: Finite State Machine. VHDL Description and Simulation (cont.)
01h00'
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation.
02h00'
Wednesday, 24 March 2010
09:00
10:00
Fourier Theory II.
01h00'
Marcelo Magnasco
10:00
11:00
Introduction to Digital Signal Processing.
01h00'
Marcelo Magnasco
11:00
11:30
Coffee break
30'
11:30
12:30
Advanced FPGA Applications.
01h00'
Alexander Kluge
CERN, Geneva, Switzerland
12:30
14:00
Lunch
01h30'
14:00
15:00
A case study in HEP experiments I.
01h00'
Alexander Kluge
15:00
16:00
Laboratory Exercises: Finite State Machine. Synthesis and Post-Synthesis Simulation (cont.)
01h00'
16:00
16:30
Coffee break
30'
16:30
17:30
Hardware Description of the FPGA Development Platform.
01h00'
Carlos Sosa Paez
University of San Luis, Argentina
17:30
18:30
FPGA Implementation Example.
01h00'
Cristian Sisterna
Thursday, 25 March 2010
09:00
10:00
Digital Signal Processing I
01h00'
Marcelo Magnasco
10:00
11:00
Digital Signal Processing II
01h00'
Marcelo Magnasco
11:00
11:30
Coffee break
30'
11:30
12:30
A case study in HEP experiments II
01h00'
Alexander Kluge
12:30
14:00
Lunch
01h30'
14:00
15:00
A case study in HEP experiments III
01h00'
Alexander Kluge
15:00
16:00
Laboratory Exercises: Implementation in the FPGA Development Platform.
01h00'
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: Implementation in the FPGA Development Platform (contd.)
02h00'
Friday, 26 March 2010
09:00
10:00
Selected topics on Logic Synthesis and FPGA Debugging.
01h00'
Andres Cicuttin
10:00
11:00
Selected topics on Logic Synthesis and FPGA Debugging (cont.)
01h00'
Andres Cicuttin
11:00
11:30
Coffee break
30'
11:30
12:30
Reconfigurable Virtual Instrumentation (RVI) based on FPGA.
01h00'
Andres Cicuttin
12:30
14:00
Lunch
01h30'
14:00
15:00
Reconfigurable Virtual Instrumentation (RVI) based on FPGA (cont.)
01h00'
Andres Cicuttin
15:00
16:00
The µLab Virtual Panel. A design example.
01h00'
Miguel Risco Castillo
16:00
16:30
Coffee break
30'
16:30
17:30
The µLab Virtual Panel. A design example. (contd).
01h00'
17:30
18:30
Laboratory Exercises: Implementation in the FPGA Development Platform (cont.)
01h00'
Monday, 29 March 2010
09:00
10:00
Radiation Effects in Semiconductor Devices.
01h00'
Felix Palumbo
CONICET - CNEA, Buenos Aires
10:00
11:00
Radiation Effects in Semiconductor Devices.
01h00'
Felix Palumbo
11:00
11:30
Coffee break
30'
11:30
12:30
Advanced Data Acquisition and Processing System for a HEP Experiment at CERN
01h00'
Maria Liz Crespo
12:30
14:00
Lunch
01h30'
14:00
16:00
Laboratory Exercises: Digital Arithmetic.
02h00'
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: Waveform generation
02h00'
Tuesday, 30 March 2010
09:00
10:00
ICTP RVI Platform Description.
01h00'
Andres Airabella
University of San Luis, Argentina
10:00
11:00
DEMO: ICTP RVI Platform. Virtual Instruments: Waveform Generator and Digital Oscilloscope
01h00'
Miguel Risco Castillo
11:00
11:30
Coffee break
30'
11:30
12:30
Digital Signal Processing with FPGA. A Design Example: Differentiator.
01h00'
Carlos Sosa Paez
12:30
14:00
Lunch
01h30'
14:00
15:00
Digital Signal Processing with FPGA. A Design Example: Differentiator (cont.)
01h00'
Carlos Sosa Paez
15:00
16:00
Laboratory Exercises: Digital Signal Processing with FPGA.
01h00'
16:00
16:30
Coffee break
30'
16:30
18:30
Laboratory Exercises: Digital Signal Processing with FPGA. (contd.)
02h00'
Wednesday, 31 March 2010
09:00
10:00
Laboratory Exercises: Digital Signal Processing with FPGA.
01h00'
10:00
11:00
Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter).
01h00'
Andres Airabella
11:00
11:30
Coffee break
30'
11:30
12:30
Digital Signal Processing with FPGA. A Design Example using the µLab Virtual Panel (constant multiplier and level shifter) (contd).
01h00'
12:30
14:00
Lunch
01h30'
14:00
15:00
General Discussions and Concluding Remarks
01h00'
15:00
15:30
Coffee break
30'
15:30
16:30
Distribution of Diplomas of Attendance
01h00'
16:30
18:30
Get-Together Drink
02h00'
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